1. Field of the Invention
The present invention relates to an electric circuit which incorporates a semiconductor transistor and in which a clock signal is used. The present invention is directed in particular to a phase-locked-loop circuit for synchronizing the phase of a signal which is derived by a voltage controlled oscillator to the phase of a reference signal.
2. Description of the Prior Art
Recent developments in semiconductor technology have made it possible for a plurality of equipments mounted in a semiconductor integrated circuit device (hereinafter "LSI") to operate at an increasingly faster speed. Hence, a technical challenge now encountered in enhancing the operation speeds is increasing the speed with which a clock signal which specifies the operation speeds of the equipments incorporated in an LSI is externally supplied to an LSI and distributed to the equipments incorporated in the LSI.
One approach to the problem is to use a phase-locked-loop circuit (hereinafter "PLL circuit") to eliminate a signal delay which is created during distribution of the clock signal to the respective equipments. The PLL circuit is mounted in the LSI and synchronizes the phase of a clock signal which has been supplied to the equipments included in the LSI to the phase of a clock signal which is supplied from outside the LSI.
An analog PLL circuit used for such an objective is shown in FIG. 9. The circuit of FIG. 9 is disclosed in IEEE JOURNAL OF SOLID-STATE CIRCUITS, Vol. 22, No. 2, April 1987, pgs. 255 to 261.
The phase of an inner clock signal 12 to be distributed within the LSI needs to be synchronized to a reference phase of a reference clock signal 11, and therefore, is compared with the phase of the reference clock signal 11 in a phase frequency comparator 1. A charge pump circuit 2 outputs a predetermined electric charge in accordance with a phase difference between the two clock signals. The electric charge is accumulated and consequently smoothed in a loop filter 3 which comprises resistors 301 and 302 and a capacitor 303. A potential V.sub.VCO which corresponds to the phase difference between the inner clock signal 12 and the reference clock signal 11 is applied to a voltage controlled oscillator (hereinafter "VCO") 4. Based on the potential V.sub.VCO, the VCO 4 generates a basic clock signal which has a frequency corresponding to the phase difference between the inner clock signal 12 and the reference clock signal 11. Receiving the basic clock signal, a clock signal generator 5 generates various clocks including the inner clock signal 12. That is, the inner clock signal 12 is fed back and synchronized to the reference clock signal 11 to thereby stabilize the phase of the inner clock signal 12.
In such a conventional PLL circuit, first, the frequency of the reference clock signal 11 is determined according to a user's instruction, and then the loop filter 3, the VCO 4 and the other elements are designed to accommodate to the decided frequency. Following this, based on the design, mask patterns are formed which will be used in manufacturing the PLL circuit. Thus, the conventional PLL circuit is tailored especially for the user according to the user's instruction.
On the other hand, there is a demand for incorporating the PLL circuit in a semicustom semiconductor integrated circuit such as a gate array so that equipments formed by the gate array are provided with a signal which is synchronized to an external clock signal which is supplied from the PLL circuit. However, since different users use different external clock signal frequencies, if the PLL circuit is to be incorporated in the gate array, special design for the loop filter 3 and the like is necessary to attain the clock signal frequency which is demanded by the user. This directly contradicts the desired flexibility of the gate array, that is, the major blessing of the gate array.
In addition, a large area is needed to form the capacitor 303 in the loop filter 3, which makes it impossible to enhance the device density.